1. Field of the Invention
The present invention generally relates to computer architectures. More particularly, the present invention relates to caching I/O requests in a computer system.
2. Description of the Related Art
Modern computer systems are often designed based on a modular architecture, allowing individual extension modules to be added to a computer system based on the specific requirements of the system. Extension modules vary widely and may include peripheral as well as internal extension devices or adapter cards, such as network interface cards, graphic boards or storage controllers, among others.
In particular, the last kind of extension modules, i.e. adapter cards, referred to as I/O components in the remainder of this application, are usually installed using high-speed connectors, such as the peripheral component interconnect express interface (PCIe), in close functional, electrical and spatial proximity to core system components such as the main processor, also referred to as CPU, and the main memory. Such an arrangement allows I/O components to operate at a very high speed and, at least in part, independently from the main processor.
However, due to the limitations in both space and electrical connectors available for I/O components in a casing of a computer system, some computer systems make use of an expansion unit in order to accommodate further I/O components. Such computer systems including a main unit and at least one expansion unit are particularly useful for larger server systems, including a multiplicity of I/O components.
One limitation of such computer systems is the latency added by the extended signaling path and driver electronic connecting the main unit and the expansion unit.
Some related art documents are concerned with accessing and caching requests to input/output components. Among those, patent U.S. Pat. No. 7,076,575 B2 to Baitinger et al. teaches a method for accessing input/output devices in embedded control environments. Further, patent application US 2006/0143333 A1 by Minturn et al. describes an apparatus and a method for enabling cacheable writes to registers of input/output device. Patent U.S. Pat. No. 7,010,626 B2 to Kahle discloses a method and apparatus for prefetching data from a system memory to a cache for direct memory access (DMA). Finally, patent U.S. Pat. No. 6,954,807 B2 to Shih discloses a method and a DMA controller for transferring data packets from a memory to a network interface card.
It is a challenge to describe improved computer systems and methods of operation for such systems providing particularly high performance communication between a main unit and an expansion unit. The present invention provides such a systems and methods of its operation providing, particularly, high performance communication between a main unit and an expansion unit.